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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">HSTR, Hyp System Trap Register</h1><p>The HSTR characteristics are:</p><h2>Purpose</h2>
        <p>Controls trapping to Hyp mode of Non-secure accesses, at EL1 or lower, to System registers in the coproc == <span class="binarynumber">0b1111</span> encoding space:</p>

      
        <ul>
<li>By the CRn value used to access the register using MCR or MRC instruction.
</li><li>By the CRm value used to access the register using MCRR or MRRC instruction.
</li></ul>
      <h2>Configuration</h2><p>AArch32 System register HSTR bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-hstr_el2.html">HSTR_EL2[31:0]</a>.</p><p>This register is present only when EL2 is capable of using AArch32. Otherwise, direct accesses to HSTR are <span class="arm-defined-word">UNDEFINED</span>.</p>
        <p>If EL2 is not implemented, this register is <span class="arm-defined-word">RES0</span> from EL3.</p>
      <h2>Attributes</h2>
        <p>HSTR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="16"><a href="#fieldset_0-31_16">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_15">T15</a></td><td class="lr" colspan="1"><a href="#fieldset_0-14_14">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-13_13">T13</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-12_12">T12</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-11_11">T11</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-10_10">T10</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-9_9">T9</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-8_8">T8</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-7_7">T7</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-6_6">T6</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-5_5">T5</a></td><td class="lr" colspan="1"><a href="#fieldset_0-4_4">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-3_3">T3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-2_2">T2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-1_1">T1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-0_0">T0</a></td></tr></tbody></table><h4 id="fieldset_0-31_16">Bits [31:16, 14, 4]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-15_15">T&lt;n&gt;, bit [n], for n = 15, 13 to 5, 3 to 0</h4><div class="field">
      <p>The remaining fields control whether Non-secure EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == <span class="binarynumber">0b1111</span> encoding space are trapped to Hyp mode:</p>
    <table class="valuetable"><tr><th>T&lt;n&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control has no effect on Non-secure EL0 or EL1 accesses to System registers.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>Any Non-secure EL1 MCR or MRC access with coproc == <span class="binarynumber">0b1111</span> and CRn == &lt;n&gt; is trapped to Hyp mode. A Non-secure EL0 MCR or MRC access with these values is trapped to Hyp mode only if the access is not <span class="arm-defined-word">UNDEFINED</span> when the value of this field is 0.</p>
<p>Any Non-secure EL1 MCRR or MRRC access with coproc == <span class="binarynumber">0b1111</span> and CRm == &lt;n&gt; is trapped to Hyp mode. A Non-secure EL0 MCRR or MRRC access with these values is trapped to Hyp mode only if the access is not <span class="arm-defined-word">UNDEFINED</span> when the value of this field is 0.</p></td></tr></table><p>For example, when HSTR.T7 is 1, for instructions executed at Non-secure EL1:</p>
<ul>
<li>An MCR or MRC instruction with coproc set to <span class="binarynumber">0b1111</span> and &lt;CRn&gt; set to c7 is trapped to Hyp mode.
</li><li>An MCRR or MRRC instruction with coproc set to <span class="binarynumber">0b1111</span> and &lt;CRm&gt; set to c7 is trapped to Hyp mode.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Warm reset:<ul>
            <li>When the PE resets into EL2 or EL3,
            this field resets to
            <span class="binarynumber">0</span>.
</li>
          
            <li>Otherwise,
            this field resets to
            an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li>
          </ul></li></ul></div><div class="access_mechanisms"><h2>Accessing HSTR</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b100</td><td>0b0001</td><td>0b0001</td><td>0b011</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T1 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T1 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    R[t] = HSTR;
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' then
        UNDEFINED;
    else
        R[t] = HSTR;
                </p><h4 class="assembler">MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b100</td><td>0b0001</td><td>0b0001</td><td>0b011</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T1 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T1 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    HSTR = R[t];
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' then
        UNDEFINED;
    else
        HSTR = R[t];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:05; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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